最近Design team有HC，新open了職位給應(yīng)屆，主要是做數(shù)字信號(hào)處理的RTL設(shè)計(jì)，機(jī)會(huì)難得，欲購(gòu)從速哦，請(qǐng)把簡(jiǎn)歷發(fā)到alex.shen@lsi.com，下面是JD：
Job Description
- Working with an Architecture/Algorithm Development Team to finalize system architecture
- for optimal implementation of digital signal processing algorithms, including architectural definition and tradeoffs, die size, power estimation.
Requirements/Qualifications (Education)
- Digital logic design, verilog coding, logic synthesis, both RTL and gate level verification,formal verification and static timing analysis. Unix shell, Perl scripting, C/RTL co-simulation.
- Solid theory background of communication and Digital signal processing