北京中天聯(lián)科科技有限公司2015校園招聘信息

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    中天聯(lián)科2015校園招聘
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    2015校園招聘職位:
    1、ASIC Front-End Engineer
    Location: Beijing, China / Number: 8
    Responsibilities:
    Design blocks for highly complex digital communication and multimedia SoCs
    Block/System level verification
    FPGA prototyping
    Qualifications:
    Master Degree in CS or EE or equivalent
    Proficient in Digital IC design FE flow is a must (e.g. RTL coding, verification, synthesis, DFT insertion and timing analysis)
    Skill with simulator is a must (e.g. ncsim and vcs)
    Ability of programming shell/perl/tcl scripts under Linux OS
    Knowledge of Video Image Coding/Decoding/Processing/algorithm is a big plus.
    C/C++ experience is a plus.
    Good understanding of advanced verification methodologies, UVM/VMM is a strong plus
    Good understanding of complex high-speed peripheral interface is a strong plus, such as USB/Ethernet
    English level: CET-6
    A good team-player with open-minded and proactive working style
    2、Physical Design Engineer
    Location: Beijing, China / Number: 8
    Responsibilities:
    RTL synthesis
    Large scale Integrated Circuit Place & Route with advance technology nodes (like 40nm)
    Timing analysis and fixing, timing signoff
    Design for Test
    Physical Signoff (DRC & LVS)
    Deliver SOC chips within schedule
    Qualifications:
    MUST HAVE:
    Have clear and good concept for digital IC design, including timing and semiconductor knowledge.
    Good team-player with open-minded and proactive working style
    Good communication skills in English both writing and verbal
    BSEE or above in related field
    NICE TO HAVE:
    Experiences in EDA tools, specially Place and Route tools is a strong plus
    Experiences in IC design is a strong plus
    Experience in Unix/Linux working environment is a plus
    Experience in TCL, Perl language is a plus
    3、Analog Design Engineer
    Location: Beijing, China / Number: 8
    Responsibilities:
    Design analog or RF building blocks (such as ADC/DAC/PLL/analog filter/LNA/PA/Mixer etc) in deep sub-micro process
    Supervise layout and do post-layout simulations
    Characterization and debugging for the analog/RF blocks
    Qualifications:
    PhD EE or MSEE with Outstanding work in RF/analog design required
    A solid track record in deep sub-micro CMOS RFIC design with experience to involve in the analog/RF
    IC circuit from design to mass production (at least 2 productions in last 5 years)
    3 to 8 years of direct work experience with CMOS analog with 3+ year experience in < 65nm (graduate research work in university can be counted).
    Familiar with Cadence Virtuoso, Spectre RF, and similar tools
    In depth knowledge of one of the following area:
    - High performance CMOS analog design experience for communications
    - Design experience in analog-to-digital converter (ADC), mainly high speed/high resolution
    - SAR and sigma delta
    - Design experience in digital-to-analog converter (DAC) for driving high precision output, such a 50ohm line driver.
    - Design experience in high performance analog filter etc.
    - Design experience for high performance low jitter PLL (analog or all-digital);
    - Design experience in Serdes and timing circuits such as PLL, CDR, TX and RX functions.
    - Design experience in other analog functions is a plus, such as bandgap, regulator, crystal oscillator,etc.
    4、Software Engineer
    Location: Beijing&Tianjin, China / Number: 8
    Responsibilities:
    Provide differentiating software solutions based on Availink IC products
    Customize software solutions that best address customers’ needs
    Test and analysis software offerings with well defined methodologies
    Develop manuals and tools for software customization
    Qualifications:
    Solid understanding in computer technologies including operating system, system architecture, data structure, etc.
    Strong background in communication or electronic system, especially in modulation and demodulation
    Experience with participation in real software projects
    Experience with embedded software is a plus
    Knowledge of software engineering is a plus
    Knowledge of embedded hardware is a plus
    Able to read and write documents in English
    A good team-player with open-minded and proactive working style
    BS or above
    5、Hardware Engineer
    Location: Beijing, China / Number: 5
    Responsibilities:
    Identify the customers’ requirements. Deliver and improve system hardware reference designs, related documents and application notes for customers’ evaluation, design-in, and migration to mass production
    Assist on validation and test of Availink’s SoC products
    Analyzing and resolving technical issues
    Qualifications:
    BSEE or above in related fields
    Solid knowledge and good understanding both in analog & digital circuit or communication
    Basic communication knowledge
    Able to analyze and resolve technical issue independently
    Good communication skills in English both writing and verbal
    Good embedded circuits design capability. Experience in this field is a plus
    Familiar with PADs or Protel or Candence EDA Tools is a plus
    6、QA Engineer
    Location: Beijing, China / Number: 9
    Responsibilities:
    Analyze requirements specifications to create optimal test plans and strategies.
    Develop, execute, and validate test cases and scripts to support the test automation strategy
    Produce defect descriptions to quantify problems to a high degree and work with Development team on the resolution.
    Familiar with software agile methodology; QA process and practice
    Qualifications:
    Some experience in software development
    Experience developing test automation
    Experience with C/C++, MySQL, and basic scripting languages, e.g. php, python
    Strong communication (written and verbal), interpersonal, and teamwork skills
    Strong analytical, problem solving and organizational skills
    BS or above; BSEE/BSCS is prefer
    招聘流程:
    
    投遞簡(jiǎn)歷注意事項(xiàng):
    招聘范圍:全國(guó)各高校
    招聘人數(shù):50
    簡(jiǎn)歷投遞日期:9-12月
    投遞方式:發(fā)送中英文簡(jiǎn)歷至campus2015@availink.com,且將郵件主題命名為“學(xué)校-學(xué)歷-專業(yè)-姓名-應(yīng)聘職位”。